HrdWyr Careers | Innovate Analog & Digital Semiconductor Design

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Analog IP Design

Full time

Bachelors/ Masters in EE/ECE

Analog IP Design

Posted 2 days ago

Digital IP Design

Full time

Bachelors/ Masters in EE/ECE

Analog IP Design

Posted 2 days ago

IP & SoC Verification

Full time

Bachelors/ Masters in EE/ECE

Analog IP Design

Posted 2 days ago

SoC Architecture

Full time

Bachelors/ Masters in EE/ECE

Analog IP Design

Posted 2 days ago

SoC Front End Integration

Full time

Bachelors/ Masters in EE/ECE

Analog IP Design

Posted 2 days ago

SoC Physical Design

Full time

Bachelors/ Masters in EE/ECE

Analog IP Design

Posted 2 days ago

Job Function: Analog IP Design

Job Description

Define Specifications, Design and Layout of Analog IPs.
Design and Validate multiple Analog IPs like Data Converters, Power Management, Battery Charging Circuits, PLLs, Oscillators, General SoC Components, IO and Serial Interfaces.

Experience and Skills Required

5 to 15 years of experience in Analog IP Design.
Experience in High Performance, SAR ADC, Delta-Sigma Data ADCs, DACs, DC-DC converters, PLLs, I/O, Bandgap and other generic IP Design and Layout.
In-depth understanding of low power, low noise circuits design techniques, ESD, IBIS Model Generation, Package and Board interface Simulations.
Expertise in different simulation tools including Monte-Carlo analysis.
Experience in Matlab modelling is preferred.
Experience in AMS Simulations at SoC and System Level.

Soft Skills

Strong analytical, problem-solving, and hands-on skills.
Self-driven and thrives when facing open-ended tasks.
Start-up mentality: fast-paced, flexible and team-oriented.
Good written and verbal communication skills with great documentation skills.
Flexibility to work with varied schedules and tolerance for ambiguity.

Note: Please attach your resume while
applying via email.

Apply now

Job Function: Digital IP Design

Job Description

Development of Specifications, Micro Architecture, RTL Development for Digital IPs.
Setup and use standard EDA tools for Verification, Lint CDC, Synthesis, Power Analysis tools for Verification and Ensuring PPA for IP developed.
Conduct Reviews for Documentation, RTL and Verification Tests.

Experience and Skills Required

5 to 15 years of experience in SoC/IP Design.
Expertise in Writing Detailed IP Specifications, Micro Architecture, IP design, Subsystem and SoC level integration.
Expertise on RTL Development. Follow Coding Standards, expertise on Lint, CDC tools, verification and debugging of test cases, code and functional coverage analysis.
In-depth knowledge of Clocking Methodology, Low Power Implementation.
Hands on experience on writing constraints and exceptions, performing Synthesis, Timing Analysis and Design for Test Implementation.
Experience of power partitioning and usage of CPF/UPF.
Exposure to IP Design for ARM Microcontrollers based SoCs.
Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB).
Knowledge of one or more of the interface protocols, PCIe, DDR, Ethernet, I2C, UART, SPI.
Experience in Matlab Simulations and Implementing Signal Processing IPs like Digital Filters, Math Functions or FFT engines.
Experience in developing Security IPs for various Encryption standards.
Experience in implementing On-chip Memory and Flash controllers.

Soft Skills

Strong analytical, problem-solving, and hands-on skills.
Self-driven and thrives when facing open-ended tasks.
Start-up mentality: fast-paced, flexible and team-oriented.
Good written and verbal communication skills with great documentation skills.
Flexibility to work with varied schedules and tolerance for ambiguity.

Note: Please attach your resume while
applying via email.

Apply now

Job Function: IP & SoC Verification

Job Description

Develop Detailed Documentation for Verification Strategy and Test Plan for IP, Subsystem and SoC.
Directed and Random Verification at IP, Subsystem and SoC Level for complex ARM / RISC-V processor based MCU, MPU products, Mixed Signal SoCs, Processors, Memory Subsystems, Connectivity Platforms, Analog, Security Acceleration, General Peripherals.
Perform Functional and Code Coverage Analysis.

Experience and Skills Required

5 to 15 years of experience in IP & SoC Verification.
Expertise in Verilog, System Verilog, UVM, Constrained Random Verification, Formal Verification, Mixed Signal Verification, Post-Layout Gate Level Simulations, Code Coverage and Functional Coverage analysis.
Development of Verification IP and Testbenches.
Experience with AMS simulations desired.
Must have strong debug and analytical capabilities, root cause analysis.
In-depth understanding of SoC Design Flow, RTL Implementation, Analog Circuit models.

Soft Skills

Strong analytical, problem-solving, and hands-on skills.
Self-driven and thrives when facing open-ended tasks.
Start-up mentality: fast-paced, flexible and team-oriented.
Good written and verbal communication skills with great documentation skills.
Flexibility to work with varied schedules and tolerance for ambiguity.

Note: Please attach your resume while
applying via email.

Apply now

Job Function: SoC Architecture

Job Description

Define SoC Function, Performance requirements. Define SoC Connectivity, Interconnectivity, Memory Map, Interrupt Map, Pin Muxing, Power Management, SoC Clock Distribution, SoC Debug.
Define Data Flow and Use Cases.
Maintain SoC Die Size and Power Estimates and ensure competitive PPA.
Close collaboration with SoC Design and Verification Teams.

Experience and Skills Required

10 to 15 years of experience in SoC / IP Design, IP Architecture & SoC Architecture.
Experience with ARM Microcontrollers, Memory and Interconnect technologies.
Hands-on experience with defining Clocking Strategy, Power Management and Low Power strategies.
Must be familiar with various Connectivity standards, SoC Security.
Hands on experience with IP Design / Micro Architecture required.
Experience with Signal Processing IP is preferred.
Good Understanding of SoC Front End and Back End Design Flow, SoC Verification and Validation flows.
Must have deep understanding Software requirements - Secure Boot, RTOS, Device Drivers.

Soft Skills

Strong analytical, problem-solving, and hands-on skills.
Self-driven and thrives when facing open-ended tasks.
Start-up mentality: fast-paced, flexible and team-oriented.
Good written and verbal communication skills with great documentation skills.
Flexibility to work with varied schedules and tolerance for ambiguity.

Note: Please attach your resume while
applying via email.

Apply now

Job Function: SoC Front End Integration

Job Description

Front End Integration of Digital, Analog IPs and Subsystems to build complete SoC Netlist.
IOMUX and Padring generation and integration.
Design of SoC Specific Logic & IPs.
Perform quality checks like Lint and CDC at SoC level.
Implement all feedback from Verification and Physical Design teams for all changes required.
Develop SoC level Testbench for RTL and Postlayout Simulations.
Collaborate with ATE and Test teams and deliver test patterns for Probe and Package level testing.
Support Verification and Post-Silicon Debugging of issues.

Experience and Skills Required

10-15 Years Experience in front end integration for complex SoCs.
Strong scripting skills. Hands on experience in RTL coding, Lint, CDC. Experience in developing IOMUX and Padring.
Expertise in developing testbench for SoC to support directed and random verification.
Experienced with working with ATE teams for delivery of test patterns.

Soft Skills

Strong analytical, problem-solving, and hands-on skills.
Self-driven and thrives when facing open-ended tasks.
Start-up mentality: fast-paced, flexible and team-oriented.
Good written and verbal communication skills with great documentation skills.
Flexibility to work with varied schedules and tolerance for ambiguity.

Note: Please attach your resume while
applying via email.

Apply now

Job Function: SoC Physical Design

Job Description

SoC Floorplan Development, SoC Padring Integration.
Perform Physical Synthesis and Optimization, Clock Tree Synthesis and Power Partitioning and Power Distribution Network Planning. Place & Route, Custom placement and routing.
Timing Closure and Signal Integrity signoff.
Physical Verification (LVS) and Design Rule Check (DRC).
Power Integrity Signoff.
DFM / EM checks.
Work with Fab for complete Tapeout Process.

Experience and Skills Required

5 to 15 years of experience in SoC Physical Design and Chip Integration with complete RTL to GDS flow.
Expertise in Synthesis, Floor Planning, APR, building Scan Chains, Scan Re- Ordering. Custom Layout, CTS, Parasitic Extraction, Pre / Post Layout Timing Analysis, LVS, DRC, I/O Ring, ESD Integration.
In-depth understanding of low power, clock and power gating, power partitioning, IR Drop, DFM and EM rules.
Deep knowledge of Foundry Collateral and experienced in working with fab for Tapeout.

Soft Skills

Strong analytical, problem-solving, and hands-on skills.
Self-driven and thrives when facing open-ended tasks.
Start-up mentality: fast-paced, flexible and team-oriented.
Good written and verbal communication skills with great documentation skills.
Flexibility to work with varied schedules and tolerance for ambiguity.

Note: Please attach your resume while
applying via email.

Apply now